ATmega64A datasheet(121/392 Pages) ATMEL

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8160C–AVR–07/09

ATmega64A

ble buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCRnx Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is dis-

abled the CPU will access the OCRnx directly. The content of the OCR1x (Buffer or Compare)

automatically as the TCNTn – and ICRn Register). Therefore OCRnx is not read via the high

byte temporary register (TEMP). However, it is a good practice to read the low byte first as when

accessing other 16-bit registers. Writing the OCRnx registers must be done via the TEMP Regis-

ter since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be

written first. When the high byte I/O location is written by the CPU, the TEMP Register will be

updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits,

the high byte will be copied into the upper eight bits of either the OCRnx Buffer or OCRnx Com-

pare Register in the same system clock cycle.

For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”

on page 114.

15.7.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOCnx) bit. Forcing Compare Match will not set the

OCFnx flag or reload/clear the timer, but the OCnx pin will be updated as if a real Compare

Match had occurred (the COMn1:0 bits settings define whether the OCnx pin is set, cleared or

toggled).

15.7.2

Compare Match Blocking by TCNTn Write

All CPU writes to the TCNTn Register will block any Compare Match that occurs in the next timer

clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the

same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled.

15.7.3

Using the Output Compare Unit

Since writing TCNTn in any mode of operation will block all Compare Matches for one timer

clock cycle, there are risks involved when changing TCNTn when using any of the Output Com-

pare channels, independent of whether the Timer/Counter is running or not. If the value written

to TCNTn equals the OCRnx value, the Compare Match will be missed, resulting in incorrect

waveform generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP

values. The Compare Match for the TOP will be ignored and the counter will continue to

0xFFFF. Similarly, do not write the TCNTn value equal to BOTTOM when the counter is

downcounting.

The setup of the OCnx should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OCnx value is to use the Force Output Com-

pare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when

changing between waveform generation modes.

Be aware that the COMnx1:0 bits are not double buffered together with the compare value.

Changing the COMnx1:0 bits will take effect immediately.

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