ATmega64A datasheet(117/392 Pages) ATMEL

117 / 392 page

117

8160C–AVR–07/09

ATmega64A

Figure 15-2. Counter Unit Block Diagram

Signal description (internal signals):

Count

Increment or decrement TCNTn by 1.

Direction

Select between increment and decrement.

Clear

Clear TCNTn (set all bits to zero).

clk

Timer/counter clock.

TOP

Signalize that TCNTn has reached maximum value.

BOTTOM

Signalize that TCNTn has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con-

taining the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight

bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an

access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP).

The temporary register is updated with the TCNTnH value when the TCNTnL is read, and

TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the

CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.

It is important to notice that there are special cases of writing to the TCNTn Register when the

counter is counting that will give unpredictable results. The special cases are described in the

sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each Timer Clock (clk

Tn). The clkTn can be generated from an external or internal clock

source, selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 =

0) the timer is stopped. However, the TCNTn value can be accessed by the CPU, independent

of whether clk

Tn is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the Waveform Generation mode bits

(WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).

There are close connections between how the counter behaves (counts) and how waveforms

are generated on the Output Compare outputs OCnx. For more details about advanced counting

sequences and waveform generation, see “Modes of Operation” on page 123.

The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by

the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.

TEMP (8-bit)

DATA BUS (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit)

TCNTnL (8-bit)

Control Logic

Count

Clear

Direction

TOVn

(Int.Req.)

Clock Select

TOP

BOTTOM

Edge

Detector

( From Prescaler )

clk

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