ATmega32A datasheet(48/352 Pages) ATMEL

48 / 352 page

8155B–AVR–07/09

ATmega32A

$382D

out

SPL,r16

$382E

sei

; Enable interrupts

$382F

<instr>

xxx

11.1.1

Moving Interrupts Between Application and Boot Space

The General Interrupt Control Register controls the placement of the Interrupt Vector table.

11.2

11.2.1

GICR – General Interrupt Control Register

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash

memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot

Loader section of the Flash. The actual address of the start of the Boot Flash section is deter-

mined by the BOOTSZ fuses. Refer to the section “Boot Loader Support – Read-While-Write

Self-Programming” on page 252 for details. To avoid unintentional changes of Interrupt Vector

tables, a special write procedure must be followed to change the IVSEL bit:

Write the Interrupt Vector Change Enable (IVCE) bit to one.

Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled

in the cycle IVCE is set, and they remain disabled until after the instruction following the write to

IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status

Note:

If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,

interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed

in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while

executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-

Write Self-Programming” on page 252 for details on Boot Lock bits.

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by

hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable

interrupts, as explained in the IVSEL description above. See Code Example below.’

Bit

INT1

INT0

INT2

–

IVSEL

IVCE

GICR

Read/Write

R/W

Initial Value

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