ATmega32A datasheet(72/352 Pages) ATMEL

72 / 352 page

8155B–AVR–07/09

ATmega32A

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT1 is configured as a level interrupt.

• Bit 6 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set

(one). If the I-bit in SREG and the INT0 bit in GICR are set (one), the MCU will jump to the corre-

sponding interrupt vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

• Bit 5 – INTF2: External Interrupt Flag 2

When an event on the INT2 pin triggers an interrupt request, INTF2 becomes set (one). If the I-

bit in SREG and the INT2 bit in GICR are set (one), the MCU will jump to the corresponding

Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag

can be cleared by writing a logical one to it. Note that when entering some sleep modes with the

INT2 interrupt disabled, the input buffer on this pin will be disabled. This may cause a logic

change in internal signals which will set the INTF2 Flag. See “Digital Input Enable and Sleep

Modes” on page 54 for more information.

ATmega32A bảng dữ liệu(PDF) 72 Page - ATMEL Corporation