ATmega32A datasheet(246/352 Pages) ATMEL

246 / 352 page

246

8155B–AVR–07/09

ATmega32A

Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-

quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at

least five times the number of scan bits divided by the maximum hold time, t

hold,max.

24.6

ATmega32A Boundary-scan Order

Table 24-7 shows the scan order between TDI and TDO when the Boundary-scan chain is

selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The

scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in

the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the

analog circuits, which constitute the most significant bits of the scan chain regardless of which

physical pin they are connected to. In Figure 24-3, PXn. Data corresponds to FF0, PXn. Control

corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is

not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.

Table 24-6.

Algorithm for Using the ADC

Step

Actions

ADCEN

DAC

MUXEN

HOLD

PRECH

PA3.

Data

PA3.

Control

PA3.

Pullup_

Enable

SAMPLE_

PRELOAD

0x200

0x08

EXTEST

0x200

0x08

0x200

0x08

0x123

0x08

0x123

0x08

Verify the

COMP bit

scanned

out to be 0

0x200

0x08

0x200

0x08

0x200

0x08

0x143

0x08

0x143

0x08

Verify the

COMP bit

scanned

out to be 1

0x200

0x08

Table 24-7.

ATmega32A Boundary-scan Order

Bit Number

Signal Name

Module

140

AC_IDLE

Comparator

139

ACO

138

ACME

137

ACBG

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