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ATmega1284P bảng dữ liệu(PDF) 232 Page - ATMEL Corporation

tên linh kiện ATmega1284P
Giải thích chi tiết về linh kiện  8-bit Microcontroller with 128K Bytes In-System Programmable Flash
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Trang chủ  http://www.atmel.com
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ATmega1284P bảng dữ liệu(HTML) 232 Page - ATMEL Corporation

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232
8059D–AVR–11/09
ATmega1284P
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are
being addressed by the winning Master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
This is summarized in Figure 19-21. Possible status values are given in circles.
Figure 19-21. Possible Status Codes Caused by Arbitration
19.9
Register Description
19.9.1
TWBR – TWI Bit Rate Register
• Bits 7:0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See ”Bit Rate Generator
Unit” on page 213 for calculating bit rates.
19.9.2
TWCR – TWI Control Register
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
Own
Address / General Call
received
Arbitration lost in SLA
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
No
Arbitration lost in Data
Direction
Yes
Write
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
Read
B0
68/78
38
SLA
START
Data
STOP
Bit
76543210
(0xB8)
TWBR7
TWBR6
TWBR5
TWBR4
TWBR3
TWBR2
TWBR1
TWBR0
TWBR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
00000000
Bit
76543210
(0xBC)
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
TWCR
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R
R/W
Initial Value
00000000



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