ATmega1284P datasheet(174/380 Pages) ATMEL

174 / 380 page

174

8059D–AVR–11/09

ATmega1284P

OSC

System Oscillator clock frequency

UBRRn

Contents of the UBRRHn and UBRRLn Registers, (0-4095)

Some examples of UBRRn values for some system clock frequencies are found in Table 17-9 on

page 194.

17.4.2

Double Speed Operation (U2Xn)

The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has

effect for the asynchronous operation. Set this bit to zero when using synchronous operation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling

the transfer rate for asynchronous communication. Note however that the Receiver will in this

case only use half the number of samples (reduced from 16 to 8) for data sampling and clock

recovery, and therefore a more accurate baud rate setting and system clock are required when

this mode is used. For the Transmitter, there are no downsides.

17.4.3

External Clock

External clocking is used by the synchronous slave modes of operation. The description in this

section refers to Figure 17-2 on page 173 for details.

External clock input from the XCKn pin is sampled by a synchronization register to minimize the

chance of meta-stability. The output from the synchronization register must then pass through

an edge detector before it can be used by the Transmitter and Receiver. This process intro-

Table 17-1.

Equations for Calculating Baud Rate Register Setting

Operating Mode

Equation for Calculating Baud

Rate(1)

Equation for Calculating UBRR

Value

Asynchronous Normal

mode (U2Xn = 0)

Asynchronous Double

Speed mode (U2Xn = 1)

Synchronous Master

mode

BAUD

OSC

16 UBRRn

()

------------------------------------------

UBRRn

OSC

16BAUD

------------------------

–

BAUD

OSC

8 UBRRn

()

---------------------------------------

UBRRn

OSC

8BAUD

--------------------

–

BAUD

OSC

2 UBRRn

()

---------------------------------------

UBRRn

OSC

2BAUD

--------------------

–

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