ATmega1284P datasheet(151/380 Pages) ATMEL

151 / 380 page

151

8059D–AVR–11/09

ATmega1284P

Figure 15-11 on page 151 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.

Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f

clk_I/O/8)

15.9

Asynchronous Operation of Timer/Counter2

When Timer/Counter2 operates asynchronously, some considerations must be taken.

• Warning: When switching between asynchronous and synchronous clocking of

Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe

procedure for switching clock source is:

Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.

Select clock source by setting AS2 as appropriate.

Write new values to TCNT2, OCR2x, and TCCR2x.

To switch to asynchronous operation: Wait for TCN2UB, OCR2xUB, and TCR2xUB.

Clear the Timer/Counter2 Interrupt Flags.

Enable interrupts, if needed.

• The CPU main clock frequency must be more than four times the Oscillator frequency.

• When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a

temporary register, and latched after two positive edges on TOSC1. The user should not write

a new value before the contents of the temporary register have been transferred to its

destination. Each of the five mentioned registers have their individual temporary register, which

means that e.g. writing to TCNT2 does not disturb an OCR2x write in progress. To detect that a

transfer to the destination register has taken place, the Asynchronous Status Register – ASSR

has been implemented.

• When entering Power-save or ADC Noise Reduction mode after having written to TCNT2,

OCR2x, or TCCR2x, the user must wait until the written register has been updated if

Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode

before the changes are effective. This is particularly important if any of the Output Compare2

interrupt is used to wake up the device, since the Output Compare function is disabled during

writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

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