ATtiny43U datasheet(60/182 Pages) ATMEL

60 / 182 page

8048B–AVR–03/09

ATtiny43U

If low level interrupt is selected, the low level must be held until the completion of the currently

executing instruction to generate an interrupt.

10.3.2

GIMSK – General Interrupt Mask Register

• Bits 7, 3:0 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU

Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-

ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even

if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is

executed from the INT0 Interrupt Vector.

• Bit 5 – PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1

Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.

• Bit 4 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.

The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-

rupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.

10.3.3

GIFR – General Interrupt Flag Register

• Bits 7, 3:0 – Res: Reserved Bits

These bits are reserved and will always read zero.

Table 10-2.

Interrupt 0 Sense Control

ISC01

ISC00

Description

The low level of INT0 generates an interrupt request asynchronously

Any logical change on INT0 generates an interrupt request asynchronously

The falling edge of INT0 generates an interrupt request asynchronously

The rising edge of INT0 generates an interrupt request asynchronously

Bit

543

0x3B (0x5B)

–

INT0

PCIE1

PCIE0

–

GIMSK

Read/Write

R/W

Initial Value

Bit

543

0x3A (0x5A)

–

INTF0

PCIF1

PCIF0

––

GIFR

Read/Write

R/W

Initial Value

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