ATtiny43U datasheet(53/182 Pages) ATMEL

53 / 182 page

8048B–AVR–03/09

9.8.1.2

Safety Level 2

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A

timed sequence is needed when changing the Watchdog Time-out period. To change the

Watchdog Time-out, the following procedure must be followed:

In the same operation, write a logical one to WDCE and WDE. Even though the WDE

always is set, the WDE must be written to one to start the timed sequence.

Within the next four clock cycles, in the same operation, write the WDP bits as desired,

but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

9.8.2

Code Example

The following code example shows one assembly and one C function for turning off the WDT.

The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that

no interrupts will occur during execution of these functions.

Note:

1. See “Code Examples” on page 6.

Assembly Code Example(1)

WDT_off:

wdr

; Clear WDRF in MCUSR

ldi

r16, (0<<WDRF)

out

MCUSR, r16

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional Watchdog Reset

r16, WDTCR

ori

r16, (1<<WDCE)|(1<<WDE)

out

WDTCR, r16

; Turn off WDT

ldi

r16, (0<<WDE)

out

WDTCR, r16

ret

C Code Example(1)

void

WDT_off(void)

{

_WDR();

/* Clear WDRF in MCUSR */

MCUSR = 0x00

/* Write logical one to WDCE and WDE */

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

}

ATtiny43U bảng dữ liệu(PDF) 53 Page - ATMEL Corporation

ATtiny43U bảng dữ liệu(HTML) 53 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL