ATtiny43U datasheet(144/182 Pages) ATMEL

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144

8048B–AVR–03/09

ATtiny43U

The XA1/XA0 pins determine the action executed when the CLKI pin is given a positive pulse.

The bit coding is shown in Table 19-12.

When pulsing WR or OE, the command loaded determines the action executed. The different

Commands are shown in Table 19-13.

19.6

Parallel Programming

19.6.1

Enter Programming Mode

The following algorithm puts the device in parallel programming mode:

Apply 4.5 - 5.5V between V

CC and GND.

Set RESET to “0” and toggle CLKI at least six times.

Set the Prog_enable pins listed in Table 19-11 on page 143 to “0000” and wait at least

100 ns.

Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after

+12V has been applied to RESET, will cause the device to fail entering programming

mode.

Wait at least 50 µs before sending a new command.

19.6.2

Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient

programming, the following should be considered.

Table 19-12. XA1 and XA0 Coding

XA1

XA0

Action when CLKI is Pulsed

Load Flash or EEPROM Address (High or low address byte determined by BS1).

Load Data (High or Low data byte for Flash determined by BS1).

Load Command

No Action, Idle

Table 19-13. Command Byte Bit Coding

Command Byte

Command Executed

1000 0000

Chip Erase

0100 0000

Write Fuse bits

0010 0000

Write Lock bits

0001 0000

Write Flash

0001 0001

Write EEPROM

0000 1000

Read Signature Bytes and Calibration byte

0000 0100

Read Fuse and Lock bits

0000 0010

Read Flash

0000 0011

Read EEPROM

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