ATtiny24-20SSU datasheet(32/236 Pages) ATMEL

32 / 236 page

8006H–AVR–10/09

ATtiny24/44/84

Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,

the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to

“0011”, giving a division factor of eight at start up. This feature should be used if the selected

clock source has a higher frequency than the maximum frequency of the device at the present

operating conditions. Note that any value can be written to the CLKPS bits regardless of the

CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is

chosen if the selcted clock source has a higher frequency than the maximum frequency of the

device at the present operating conditions. The device is shipped with the CKDIV8 Fuse

programmed.

Table 6-11.

Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

0000

0001

0010

0011

0100

0101

0110

0111

128

1000

256

1001

Reserved

1010

Reserved

1011

Reserved

1100

Reserved

1101

Reserved

1110

Reserved

1111

Reserved

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