ATtiny24-20SSU datasheet(82/236 Pages) ATMEL

82 / 236 page

8006H–AVR–10/09

ATtiny24/44/84

Table 11-6 shows COM0B1:0 bit functionality when WGM02:0 bits are set to fast PWM mode.

Note:

1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on

page 75 for more details.

Table 11-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Note:

1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 77 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bits 1:0 – WGM01:0: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 11-8. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of

Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 74).

Table 11-6.

Compare Output Mode, Fast PWM Mode

(1)

COM0B1

COM0B0

Description

Normal port operation, OC0B disconnected.

Reserved

Clear OC0B on Compare Match, set OC0B at BOTTOM

(non-inverting mode)

Set OC0B on Compare Match, clear OC0B at BOTTOM

(inverting mode)

Table 11-7.

Compare Output Mode, Phase Correct PWM Mode(1)

COM0B1

COM0B0

Description

Normal port operation, OC0B disconnected.

Reserved

Clear OC0B on Compare Match when up-counting. Set OC0B on

Compare Match when down-counting.

Set OC0B on Compare Match when up-counting. Clear OC0B on

Compare Match when down-counting.

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