ATmega165 datasheet(148/336 Pages) ATMEL

148 / 336 page

148

ATmega165/V

2573G–AVR–07/09

USART

The Universal Synchronous and Asynchronous serial Receiver and Transmitter

(USART) is a highly flexible serial communication device. The main features are:

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

The PRUSART0 bit in “Power Reduction Register - PRR” on page 34 must be written to

zero to enable USART module.

Overview

A simplified block diagram of the USART Transmitter is shown in Figure 69. CPU acces-

sible I/O Registers and I/O pins are shown in bold.

Figure 69. USART Block Diagram

(1)

Note:

1. Refer to Figure 1 on page 2, Table 32 on page 66 for USART pin placement.

PARITY

GENERATOR

UBRR[H:L]

UDR (Transmit)

UCSRA

UCSRB

UCSRC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER

RxD

TxD

CONTROL

UDR (Receive)

CONTROL

XCK

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

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