ATmega165 datasheet(147/336 Pages) ATMEL

147 / 336 page

147

ATmega165/V

2573G–AVR–07/09

Data Modes

There are four combinations of SCK phase and polarity with respect to serial data,

which are determined by control bits CPHA and CPOL. The SPI data transfer formats

are shown in Figure 67 and Figure 68. Data bits are shifted out and latched in on oppo-

site edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is

clearly seen by summarizing Table 60 and Table 61, as done below:

Figure 67. SPI Transfer Format with CPHA = 0

Figure 68. SPI Transfer Format with CPHA = 1

Table 63. CPOL Functionality

Leading Edge

Trailing eDge

SPI Mode

CPOL=0, CPHA=0

Sample (Rising)

Setup (Falling)

CPOL=0, CPHA=1

Setup (Rising)

Sample (Falling)

CPOL=1, CPHA=0

Sample (Falling)

Setup (Rising)

CPOL=1, CPHA=1

Setup (Falling)

Sample (Rising)

Bit 1

Bit 6

LSB

MSB

SCK (CPOL = 0)

mode 0

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 2

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

MSB first (DORD = 0)

LSB first (DORD = 1)

SCK (CPOL = 0)

mode 1

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 3

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

MSB first (DORD = 0)

LSB first (DORD = 1)

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