ATmega128 datasheet(264/386 Pages) ATMEL

264 / 386 page

264

2467S–AVR–07/09

ATmega128

Note:

Incorrect setting of the switches in Figure 131 will make signal contention and may damage the

part. There are several input choices to the S&H circuitry on the negative input of the output com-

parator in Figure 131. Make sure only one path is selected from either one ADC pin, Bandgap

reference source, or Ground.

If the ADC is not to be used during scan, the recommended input values from Table 104 should

be used. The user is recommended not to use the Differential Gain stages during scan. Switch-

Cap based gain stages require fast operation and accurate timing which is difficult to obtain

when used in a scan chain. Details concerning operations of the differential gain stage is there-

fore not provided.

The AVR ADC is based on the analog circuitry shown in Figure 131 with a successive approxi-

mation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is

usually to ensure that an applied analog voltage is measured within some limits. This can easily

be done without running a successive approximation algorithm: apply the lower limit on the digi-

tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit

on the digital DAC[9:0] lines, and verify the output from the comparator to be high.

The ADC need not be used for pure connectivity testing, since all analog inputs are shared with

a digital port pin as well.

When using the ADC, remember the following

•

The Port Pin for the ADC channel in use must be configured to be an input with pull-up

disabled to avoid signal contention.

•

In normal mode, a dummy conversion (consisting of 10 comparisons) is performed when

enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before

controlling/observing any ADC signal, or perform a dummy conversion before using the first

result.

•

The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal

low (Sample mode).

As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when

the power supply is 5.0V and AREF is externally connected to V

CC.

SCTEST

Input

Switch-cap TEST

enable. Output from

x10 gain stage send

out to Port Pin having

ADC_4

Input

Output of gain stages

will settle faster if this

signal is high first two

ACLK periods after

AMPEN goes high.

VCCREN

Input

Selects Vcc as the

ACC reference

voltage.

Table 104. Boundary-scan Signals for the ADC (Continued)

Signal

Name

Direction

as Seen

from the

ADC

Description

Recommen-

ded Input

when not

in Use

Output Values when

Recommended Inputs

are Used, and CPU is

not Using the ADC

The lower limit is:

1024 1.5

V 0,95 5V

⁄

⋅⋅

291

0x123

The upper limit is:

1024 1.5

V 1.05 5V

⁄

⋅⋅

323

0x143

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