ATmega128 datasheet(158/386 Pages) ATMEL

158 / 386 page

158

2467S–AVR–07/09

ATmega128

Table 66 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM

mode.

Note:

1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare

match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 152

for more details.

Table 67 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct

PWM mode.

Note:

1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare

match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page

153 for more details.

• Bit 2:0 – CS22:0: Clock Select

The three clock select bits select the clock source to be used by the Timer/Counter.

Table 65. Compare Output Mode, Non-PWM Mode

COM21

COM20

Description

Normal port operation, OC2 disconnected.

Toggle OC2 on compare match

Clear OC2 on compare match

Set OC2 on compare match

Table 66. Compare Output Mode, Fast PWM Mode

(1)

COM21

COM20

Description

Normal port operation, OC2 disconnected.

Reserved

Clear OC2 on compare match, set OC2 at BOTTOM,

(non-inverting mode)

Set OC2 on compare match, clear OC2 at BOTTOM,

(inverting mode)

Table 67. Compare Output Mode, Phase Correct PWM Mode(1)

COM21

COM20

Description

Normal port operation, OC2 disconnected.

Reserved

Clear OC2 on compare match when up-counting. Set OC2 on compare

match when downcounting.

Set OC2 on compare match when up-counting. Clear OC2 on compare

match when downcounting.

Table 68. Clock Select Bit Description

CS22

CS21

CS20

Description

No clock source (Timer/Counter stopped)

001

clkI/O/(No prescaling)

010

clkI/O/8 (From prescaler)

011

clkI/O/64 (From prescaler)

100

clkI/O/256 (From prescaler)

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