ATmega128 datasheet(106/386 Pages) ATMEL

106 / 386 page

106

2467S–AVR–07/09

ATmega128

Note:

1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare

match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page

101 for more details.

• Bit 2:0 – CS02:0: Clock Select

The three clock select bits select the clock source to be used by the Timer/Counter, see Table

56.

Timer/Counter

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare

match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,

introduces a risk of missing a compare match between TCNT0 and the OCR0 Register.

Output Compare

The Output Compare Register contains an 8-bit value that is continuously compared with the

counter value (TCNT0). A match can be used to generate an output compare interrupt, or to

generate a waveform output on the OC0 pin.

Table 55. Compare Output Mode, Phase Correct PWM Mode(1)

COM01

COM00

Description

Normal port operation, OC0 disconnected.

Reserved

Clear OC0 on compare match when up-counting. Set OC0 on compare

match when downcounting.

Set OC0 on compare match when up-counting. Clear OC0 on compare

match when downcounting.

Table 56. Clock Select Bit Description

CS02

CS01

CS00

Description

No clock source (Timer/Counter stopped)

clk

T0S/(No prescaling)

clk

T0S/8 (From prescaler)

clk

T0S/32 (From prescaler)

clk

T0S/64 (From prescaler)

clk

T0S/128 (From prescaler)

clk

0S/256 (From prescaler)

clkT0S/1024 (From prescaler)

Bit

765

4321

TCNT0[7:0]

TCNT0

Read/Write

R/W

Initial Value

000

0000

Bit

765

4321

OCR0[7:0]

OCR0

Read/Write

R/W

Initial Value

000

0000

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