EN56Q64-104FIP datasheet(21/60 Pages) EON

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This Data Sheet may be revised by subsequent versions

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or modifications due to changes in technical specifications.

EN25Q64

Rev. E, Issue Date: 2009/10/19

Table 6. Status Register Bit Locations

SRP

Status

Protect

OTP_LOCK

bit

(note 1)

WPDIS

(WP# disable)

BP3

(Block

Protected bits)

BP2

(Block

Protected bits)

BP1

(Block

Protected bits)

BP0

(Block

Protected bits)

WEL

(Write Enable

Latch)

WIP

(Write In

Progress bit)

(Note 3)

1 = status

disable

1 = OTP

sector is

protected

1 = WP#

disable

0 = WP#

enable

(note 2)

1 = write

enable

0 = not write

enable

1 = write

operation

0 = not in write

operation

Non-volatile bit

Non-volatile bit Non-volatile bit. Non-volatile bit Non-volatile bit Non-volatile bit

volatile bit

Note

1. In OTP mode, SRP bit is served as OTP_LOCK bit.

2. See the table “

Protected Area Sizes Sector Organization”.

3. When executed the (RDSR) (05h) command, the WIP (S0) value is the same as WIP (S7) in table 7.

The status and control bits of the Status Register are as follows:

WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status

cycle is in progress.

WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is

reset and no Write Status Register, Program or Erase instruction is accepted.

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define

the size of the area to be software protected against Program and Erase instructions. These bits are

written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP3,

BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected

against Page Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect

(BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.

The Chip Erase (CE) instruction is executed if, and only if, all Block Protect (BP3, BP2, BP1, BP0) bits

are 0.

WPDIS bit. The Write Protect disable (WPDIS) bit, non-volatile bit, when it is reset to “0” (factory

default) to enable WP# function or is set to “1” to disable WP# function (can be floating during SPI

mode.)

SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit operates in conjunction with the Write

Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow

the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set

to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register

(SRP, BP3, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is

no longer accepted for execution.

In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal

sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR

command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only

be programmed once.

Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,

user must clear the protect bits before enter OTP mode and program the OTP code, then execute

WRSR command to lock the OTP sector before leaving OTP mode.

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