EM68932DVKB datasheet(17/40 Pages) ETRON

17 / 40 page

EtronTech

EM68932DVKB

Etron Confidential

Rev. 1.0

Aug. 2009

2. Driver Strength should be selected based on actual system loading conditions. Figure 3, the AC Output

Load Circuit, represents the reference load used in defining the relevant timing parameters of this

device.The 20pF load capacitance is not expected to be a precise representation of either a typical system

load or the production test environment but is appropriate for Full Driver Strength. Setting the output drivers

to 1/2 Driver Strength, for a further example, is appropriate for a 10pF load.

3. The specific requirement is that DQS be Valid (High or Low) on or before this CK edge. The case shown

(DQS going from High-Z to logic Low) applies when no writes were previously in progress on the bus. If a

previous write was in progress, DQS could be High at this time, depending on tDQSS.

4. Table 14. I/O Setup / Hold Slew Rate Derating

I/O Setup/Hold Slew Rate (V/ns)

△

tDS (ps)

△

tDH (ps)

1.0

0.8

+75

0.6

+150

This derating table is used to increase tDS / tDH in the case where the I/O slew rate is below 1.0V/ns

5. Table 15. I/O Delta Rise / Fall Derating

I/O Delta Rise / Fall Rate (ns/V)

△

tDS (ps)

△

tDH (ps)

1.0

±0.25

+50

±0.50

+100

This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta

Rise / Fall Rate is calculated as 1/SlewRate1-1/SlewRate2. For example, if SlewRate1 = 1.0V/ns and

SlewRate2 = 0.8V/ns, then the Delta Rise / Fall Rate = -0.25ns/V.

6. There must be at least one clock (CK) pulse during the tXP period.

7. tWTR is referenced from the positive clock edge after the last Data In pair.

8. tWR is referenced from the positive clock edge after the last desired Data In pair.

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