LPC2917SLASH01 datasheet(49/86 Pages) NXP

49 / 86 page

LPC2917_19_01_2

Preliminary data sheet

Rev. 02 — 17 June 2009

49 of 86

NXP Semiconductors

LPC2917/01; LPC2919/01

ARM9 microcontroller with CAN and LIN

Conﬁguration of the CGU0: For every output generator generating the base clocks a

choice can be made from the primary and secondary clock generators according to

Figure 13.

Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be

connected to either a fractional divider (FDIV0..6) or to one of the outputs of the PLL or to

LP_OSC/crystal oscillator directly. BASE_SAFE_CLK and BASE_PCR_CLK can use only

LP_OSC as source.

The fractional dividers can be connected to one of the outputs of the PLL or directly to

LP_OSC/crystal Oscillator.

The PLL is connected to the crystal oscillator.

In this way every output generating the base clocks can be conﬁgured to get the required

clock. Multiple output generators can be connected to the same primary or secondary

clock source, and multiple secondary clock sources can be connected to the same PLL

output or primary clock source.

Invalid selections/programming - connecting the PLL to an FDIV or to one of the PLL

outputs itself for example - will be blocked by hardware. The control register will not be

written, the previous value will be kept, although all other ﬁelds will be written with new

data. This prevents clocks being blocked by incorrect programming.

Default Clock Sources: Every secondary clock generator or output generator is

connected to LP_OSC at reset. In this way the device runs at a low frequency after reset.

It is recommended to switch BASE_SYS_CLK to a high-frequency clock generator as one

of the ﬁrst steps in the boot code after verifying that the high-frequency clock generator is

running.

Clock Activity Detection: Clocks that are inactive are automatically regarded as invalid,

and values of ‘CLK_SEL’ that would select those clocks are masked and not written to the

control registers. This is accomplished by adding a clock detector to every clock

Fig 13. Structure of the clock generation scheme

LP_OSC

PLL

FDIV0:6

EXTERNAL

OSCILLATOR

002aad834

clkout

clkout120

clkout240

OUTPUT

CONTROL

clock

outputs

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