TMS320VC5504 datasheet(83/128 Pages) TI

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6.9.4

EMIF Electrical Data/Timing CVDD = 1.3 V, DVDDEMIF = 3.3/2.8/2.5/1.8 V

TMS320VC5504

Fixed-Point Digital Signal Processor

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SPRS609A – JUNE 2009 – REVISED JULY 2009

Table 6-13. Timing Requirements for EMIF Asynchronous Memory(1) (see Figure 6-14, Figure 6-16, and

Figure 6-17)

CVDD = 1.3 V

DVDDEMIF = 3.3/2.8/2.5/1.8 V

NO.

UNIT

MIN

NOM

MAX

READS and WRITES

tw(EM_WAIT)

Pulse duration, EM_WAITx assertion and deassertion

READS

tsu(EMDV-EMOEH)

Setup time, EM_D[15:0] valid before EM_OE high

th(EMOEH-EMDIV)

Hold time, EM_D[15:0] valid after EM_OE high

tsu(EMOEL-EMWAIT)

Setup Time, EM_WAITx asserted before end of Strobe Phase(2)

4E + 5

WRITES

tsu(EMWEL-EMWAIT)

Setup Time, EM_WAITx asserted before end of Strobe Phase(2)

4E + 5

(1)

E = SYSCLK period in ns, if EMIF is set for "full rate" or E = SYSCLK/2 period in ns, if EMIF is set for "half rate" as defined by bit 14 of

the EMIF Status register (0x1001h). For example, when EMIF is set to full rate and SYSCLK is selected and set to 100 MHz, E = 10 ns.

(2)

Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended

wait states. Figure 6-16 and Figure 6-17 describe EMIF transactions that include extended wait states inserted during the STROBE

phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where

the HOLD phase would begin if there were no extended wait cycles.

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