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6.6 Direct Memory Access (DMA) Controller

6.6.1

DMA Channel Synchronization Events

TMS320VC5504

Fixed-Point Digital Signal Processor

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SPRS609A – JUNE 2009 – REVISED JULY 2009

The DMA controller is used to move data among internal memory, external memory, and peripherals

without intervention from the CPU and in the background of CPU operation.

The DSP includes a total of four DMA controllers. Aside from the DSP resources they can access, all four

DMA controllers are identical.

The DMA controller has the following features:

• Operation that is independent of the CPU.

• Four channels, which allow the DMA controller to keep track of the context of four independent block

transfers.

• Event synchronization. DMA transfers in each channel can be made dependent on the occurrence of

selected events.

• An interrupt for each channel. Each channel can send an interrupt to the CPU on completion of the

programmed transfer.

• A dedicated clock idle domain. The four device DMA controllers can be put into a low-power state by

independently turning off their input clocks.

For more details on the DMA controller, see the TMS320VC5505 DSP Direct Memory Access (DMA)

Controller User’s Guide (literature number SPRUFO9).

The DMA controllers allow activity in their channels to be synchronized to selected events. The DSP

supports 20 separate synchronization events and each channel can be tied to separate sync events

independent of the other channels. Synchronization events are selected by programming the CHnEVT

field in the DMAn channel event source registers (DMAnCESR1 and DMAnCESR2). The synchronization

events available to each DMA controller are shown in the TMS320VC5505 DSP System User's Guide

(literature number SPRUFP0).

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