TMS77C82 datasheet(34/73 Pages) TI

34 / 73 page

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

timer 2n modules (T2A and T2B) (continued)

The timer 2n dual-compare mode block diagram is illustrated in Figure 12. The annotations on the diagram

identify the register and the bit(s) in the peripheral frame. For example, the actual address of T2nCTL2.0 is

106Bh (n = A) or 108Bh (n = B), bit 0, in the T2nCTL2 register.

T2nC.15-0

T2nCTL2.1

T2nCTL3.2

T2nCTL3.1

T2nCTL3.5

T2nCTL3.3

Clock

Source

16-Bit

Counter

16-Bit

Compare=

Reset

T2nC1

RST ENA

T2n SW

RESET

Edge 1

Select

T2nEDGE1 DET ENA

Output

Enable

Capt/Comp

MSB

LSB

MSB

LSB

T2nEDGE1

OUT ENA

T2nIC1/CR

T2nEDGE1 POLARITY

16-Bit

Compare

MSB

LSB

T2nCC.15-0

T2nC1 INT FLAG

T2nCTL2.0

T2nCTL2.5

T2nC1 INT ENA

T2nC2 INT FLAG

T2nCTL2.6

T2nC2 INT ENA

T2n OVRFL INT FLAG

T2nCTL1.4

T2n CTL1.3

T2n OVRFL INT ENA

T2nEDGE1 INT FLAG

T2nCTL2.2

T2n CTL2.7

T2nEDGE1 INT ENA

T2n PRIORITY

T2nC2 OUT ENA

T2nC1 OUT ENA

T2nCTL3.6

T2nIC2/PWM

T2nPC2.7-4

T2nPRI.6

T2nCNTR.15-0

T2nCTL1.0

T2nCTL3.4

T2nEDGE1

RST ENA

T2nPC2.3-0

T2nCTL3.0

Level 1 Int

Level 2 Int

Figure 12. Dual-Compare Mode

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