TMS320VC549 datasheet(97/111 Pages) TI

97 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

serial-port receive timing in TDM mode

timing requirements for serial-port receive in TDM mode [H = 0.5tc(CO)] (’542/’543 only)

(see Figure 38)

’542

’543

UNIT

MIN

MAX

UNIT

tc(SCK)

Cycle time, serial-port clock

†

tf(SCK)

Fall time, serial-port clock

tr(SCK)

Rise time, serial-port clock

tw(SCK)

Pulse duration, serial-port clock low/high

tsu(TD-TCL)

Setup time, TDAT/TADD before TCLK falling edge

–(3H–9)

th(TCH-TD)

Hold time, TDAT/TADD after TCLK rising edge, tw(SCKL) < 5H

th(TCL-TD)

Hold time, TDAT/TADD after TCLK falling edge, tw(SCKL) > 5H

5H+5

tsu(TF-TCH)

Setup time, TFRM before TCLK rising edge‡

th(TCH-TF)

Hold time, TFRM after TCLK rising edge‡

† The serial-port design is fully static and, therefore, can operate with tc(SCK)approachinginfinity.Itischaracterizedapproachinganinputfrequency

of 0 Hz but tested at a much higher frequency to minimize test time.

‡ TFRM timing and waveforms shown in Figure 38 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is

illustrated in the transmit timing diagram in Figure 39.

timing requirements for serial-port receive in TDM mode [H = 0.5tc(CO)] (’54x devices other than

’542/’543) (see Figure 38)

’C54x-40

’LC54x-40

’LC54x-50

’54X-66

UNIT

MIN

MAX

MIN

MAX

tc(SCK)

Cycle time, serial-port clock

†

16H

†

tf(SCK)

Fall time, serial-port clock

tr(SCK)

Rise time, serial-port clock

tw(SCK)

Pulse duration, serial-port clock low/high

tsu(TD-TCH)

Setup time, TDAT/TADD before TCLK rising edge

th(TCH-TD)

Hold time, TDAT/TADD after TCLK rising edge

–6

tsu(TF-TCH)

Setup time, TFRM before TCLK rising edge‡

th(TCH-TF)

Hold time, TFRM after TCLK rising edge‡

† The serial-port design is fully static and, therefore, can operate with tc(SCK)approachinginfinity.Itischaracterizedapproachinganinputfrequency

of 0 Hz but tested at a much higher frequency to minimize test time.

‡ TFRM timing and waveforms shown in Figure 38 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is

illustrated in the transmit timing diagram in Figure 39.

TMS320VC549 bảng dữ liệu(PDF) 97 Page - Texas Instruments

TMS320VC549 bảng dữ liệu(HTML) 97 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL