TIR2000 datasheet(20/63 Pages) TI

20 / 63 page

2–8

2.1.3

Slow-Speed Infrared (SIR) Mode (IrDA 1.0)

The SIR mode of operation is similar to the UART mode except that data communication takes place in a

slow-speed half-duplex manner. The method of data transfer is infrared instead of on a wired path. The

modem-control register (MCR) and the Modem Status Register (MSR) are not used.

Data transfer occurs with a baud rate of up to 115.2 Kbps. The format of serial data is similar to the UART

data format. Each data byte starts with a start bit (0), 1 byte of data, and then ends with at least a stop bit

(1). Each serial data bit is encoded before transmission and decoded after being received. A 1 is decoded

with no IR pulse and a 0 is decoded by sending 3/16th of one bit time IR pulse. Similarly, the received serial

pulse is decoded as a 0 and the absence of an IR pulse is decoded as a 1 (see Figure 2–2).

3/16

Transmit Data

IR Output

Figure 2–2. SIR Encoding

The following register programming steps are required to receive or transmit data in SIR mode

transmissions:

Program the ICR register.

Program the prescaler (PRESC) register to ensure the prescaler output is approximately 1.843

MHz. The default PRESC value is used for an input clock frequency of 48-MHz.

Program the auxiliary baud-rate divisor lower byte (ABDL) and the auxiliary baud-rate divisor

higher byte (ABDH) registers to select the desired communication baud rate for the UART mode.

The baud rate is given by:

Baud rate

PRESC

Divisor

(1)

Program the mode definition register (MDR) to:

•

Select the SIR mode

•

Enable/disable the low-power mode. For normal operation, the low-power mode is enabled.

•

Enable/disable the sleep mode.

2.1.3.1

SIR Data Transmission Mode

The following register programming steps are required for data transmission in the SIR mode:

Program the PLR register to select the TX FIFO trigger level.

Reset the TX FIFO and program the FCR register.

Program the IER register to enable only the data transmission interrupts.

•

Enable the TX holding-register-empty interrupt

•

Enable the TX underrun interrupt

•

Disable the RX FIFO over the threshold interrupt

•

Disable the RX FIFO overrun error interrupt

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