TIR2000 datasheet(41/63 Pages) TI

41 / 63 page

4–5

4.6

Line Status Register (LSR) – (read only)

Address: 5 (Hex)

MIR, FIR Mode

LSR

Bit No

Definition

TX empty

Status

FIFO

full

Received last

byte from RX

FIFO

Frame

length

error

PHY

error

CRC error

Status

FIFO

empty

RX FIFO

empty

Default

Bit definition:

BIT NO.

DESCRIPTIONS

Receiver FIFO empty. Bit 0 indicates the empty status of RX FIFO register. When the RX FIFO becomes

empty bit 0 becomes a 1 and when RX FIFO is not empty, it becomes a 0.

Port 1 is set to a 1 when the Status FIFO is empty.

CRC error. When a bad CRC is detected on data receive, bit 2 is set to 1. Bit 2 is cleared to 0 when the

LSR register is read.

PHY error. In FIR mode, bit 3 is set to a 1 when an illegal symbol is received during reception. In the MIR

mode, bit 3 is set to a 1 when an abort pattern (at least 7 consecutive 1’s) is received during reception. Bit

3 is cleared to a 0 when the LSR register is read.

Frame–too–long. Bit 4 is set to 1 when a frame exceeding the maximum length (set by RXFLH register and

the RXFLL register) is received. When this error is detected, current frame reception is terminated.

Reception is stopped until the next BOF is detected. Bit 4 is cleared to a 0 when the LSR register is read.

Received last byte from FIFO. Bit 5 is set to a 1 when the CPU reads the last byte of a frame. Bit 5 can be

used for software polling to determine the frame boundary. It is cleared to a 0 when the CPU reads the LSR

Bit 6 is set to a 1 when the Status FIFO is full.

Transmitter empty. When TX FIFO is empty and the transmitter front-end is idle, this bit is set to a 1.

LSR in TV Mode

LSR_TV

Bit No.

[6–2]

Description

TX FIFO empty

Not relevant

TV_IR pulse detected

RX FIFO register empty

Default

Always 0

Bit definition:

BIT NO

DESCRIPTION

When bit 0 is a 1, the RX FIFO register is empty. A 0 in bit 0 indicates the RX FIFO register is not empty.

When bit 1 is a 1, the valid IR pulse (carrier frequency within programmed range) has been detected. Bit

1 is reset to a 0 when read.

[6–2]

Not relevant

When bit 7 is a 1, the TX FIFO register is empty. A 0 in Bit 7 indicates the TX FIFO register is not empty.

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