SN74ACT3638

512

× 32 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS228D – JUNE 1992 – REVISED APRIL 1998

20

POST OFFICE BOX 655303

tpd(C-AF)

tpd(C-AF)

tsu(EN)

CLKA

AFA

ENB

ENA

tsu(EN)

th(EN)

[512 – (Y1 + 1)] Words in FIFO1

th(EN)

tsk2†

12

CLKB

(512 – Y1) Words in FIFO1

† tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition high in the next CLKA cycle. If the time

between the rising CLKA edge and rising CLKB edge is less than tsk2, then AFA may transition high one CLKB cycle later than shown.

NOTE A: FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = H, MBB = L). Data in the FIFO1 output register has been

read from the FIFO.

Figure 15. Timing for AFA When FIFO1 Is Almost Full

tpd(C-AF)

tpd(C-AF)

tsu(EN)

CLKB

AFB

ENA

ENB

tsu(EN)

th(EN)

[512 – (Y2 + 1)] Words in FIFO2

th(EN)

tsk2‡

12

CLKA

(512 – Y2) Words in FIFO2

‡ tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition high in the next CLKB cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than tsk2, then AFB may transition high one CLKA cycle later than shown.

NOTE A: FIFO2 write (CSB = L, W/RB = L, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L). Data in the FIFO2 output register has been

read from the FIFO.

Figure 16. Timing for AFB When FIFO2 Is Almost Full