APA600-FGGES datasheet(27/174 Pages) ACTEL

27 / 174 page

ProASICPLUS Flash Family FPGAs

v5.7

1-21

PLL Electrical Specifications

Parameter

Value

Notes

Frequency Ranges

Reference Frequency fIN (min.)

1.5 MHz

Clock conditioning circuitry (min.) lowest input frequency

Reference Frequency fIN (max.)

180 MHz

Clock conditioning circuitry (max.) highest input frequency

OSC Frequency fVCO (min.)

24 MHz

Lowest output frequency voltage controlled oscillator

OSC Frequency fVCO (max.)

180 MHz

Highest output frequency voltage controlled oscillator

Clock Conditioning Circuitry fOUT (min.)

6 MHz

Lowest output frequency clock conditioning circuitry

Clock Conditioning Circuitry fOUT (max.)

180 MHz

Highest output frequency clock conditioning circuitry

Long Term Jitter Peak-to-Peak Max.*

Temperature

Frequency MHz

fVCO<10

10<fVCO<60

fVCO>60

25°C (or higher)

±1%

±2%

±1%

Jitter(ps) = Jitter(%)*period

For example:

Jitter in picoseconds at 100 MHz

= 0.01 * (1/100E6) = 100 ps

0°C

±1.5%

±2.5%

±1%

–40°C

±2.5%

±3.5%

±1%

–55°C

±2.5%

±3.5%

±1%

Acquisition Time from Cold Start

Acquisition Time (max.)

μsf

VCO ≤ 40 MHz

Acquisition Time (max.)

μsf

VCO > 40 MHz

Power Consumption

Analog Supply Power (max.*)

6.9 mW per PLL

Digital Supply Current (max.)

μW/MHz

Duty Cycle

50% ±0.5%

Input Jitter Tolerance

5% input period (max. 5 ns)

Maximum jitter allowable on an input clock to

acquire and maintain lock.

Note: *High clock frequencies (>60 MHz) under typical setup conditions

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