APA600-FGGES datasheet(70/174 Pages) ACTEL

70 / 174 page

ProASICPLUS Flash Family FPGAs

1- 64

v5.7

Synchronous Write and Asynchronous Read to the Same Location

Note: The plot shows the normal operation status.

Figure 1-40 • Synchronous Write and Asynchronous Read to the Same Location

Table 1-59 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial

TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol txxx

Description

Min.

Max.

Units

Notes

ORDA

New DO access from RB

↓

7.5

ORDH

Old DO valid from RB

↓

3.0

OWRA

New DO access from WCLKS

↓

3.0

OWRH

Old DO valid from WCLKS

↓

0.5

RAWCLKS

↓ or RADDR from WCLKS ↑

5.0

RAWCLKH

↑ or RADDR from WCLKS ↓

5.0

Notes:

1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically

trigger a read operation which updates the read data.

2. Violation of RAWCLKS will disturb access to OLD data.

3. Violation of RAWCLKH will disturb access to NEWER data.

4. All –F speed grade devices are 20% slower than the standard numbers.

RB, RADDR

OLD

NEW

NEWER

tORDA

tORDH

tRAWCLKS

tRAWCLKH

WCLKS

tOWRH

tOWRA

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