AT91SAM9261 datasheet(24/43 Pages) ATMEL

24 / 43 page

6062KS–ATARM–15-Jan-09

AT91SAM9261 Preliminary

9.2

Reset Controller

• Based on two Power-on-Reset cells

• Status of the last reset

– Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset

• Controls the internal resets and the NRST pin output

9.3

Shutdown Controller

• Shutdown and Wake-up logic:

– Software programmable assertion of the SHDN pin

– Deassertion Programmable on a WKUP pin level change or on alarm

9.4

General-purpose Backup Registers

• Four 32-bit general-purpose backup registers

9.5

Clock Generator

• Embeds the Low-power 32768 Hz Slow Clock Oscillator

– Provides the permanent Slow Clock to the system

• Embeds the Main Oscillator

– Oscillator bypass feature

– Supports 3 to 20 MHz crystals

• Embeds Two PLLs

– Outputs 80 to 240 MHz clocks

– Integrates an input divider to increase output accuracy

– 1 MHz minimum input frequency

• Provides SLCK, MAINCK, PLLACK and PLLBCK.

Figure 9-2.

Clock Generator Block Diagram

Power

Management

Controller

XIN

XOUT

PLLRCA

Slow Clock

SLCK

Main Clock

MAINCK

PLLA Clock

PLLACK

Control

Status

PLL and

Divider B

PLLRCB

PLLB Clock

PLLBCK

XIN32

XOUT32

Slow Clock

Oscillator

Main

Oscillator

PLL and

Divider A

Clock Generator

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