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EPLD bảng dữ liệu(PDF) 37 Page - Altera Corporation

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Giải thích chi tiết về linh kiện  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
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EPLD bảng dữ liệu(HTML) 37 Page - Altera Corporation

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Altera Corporation
781
Classic EPLD Family Data Sheet
Operating
Conditions
Tables 23 through 27 provide information on absolute maximum ratings,
recommended operating conditions, operating conditions, and
capacitance for EP1810 devices.
Table 23. EP1810 Device Absolute Maximum Ratings
Notes (1), (2)
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
Supply voltage
With respect to ground
(3)
–2.0 (–0.5)
7.0
V
VI
DC input voltage
With respect to ground
(3)
–2.0 (–0.5)
7.0
V
IMAX
DC VCC or ground current
–300 (–400)
300 (400)
mA
IOUT
DC output current, per pin
–25
25
mA
TSTG
Storage temperature
No bias
–65
150
° C
TAMB
Ambient temperature
Under bias
–65
135
° C
TJ
Junction temperature
Ceramic packages, under bias
150
° C
Plastic packages, under bias
135
° C
Table 24. EP1810 Device Recommended Operating Conditions
Note (2)
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
Supply voltage
(4)
4.75 (4.5)
5.25 (5.5)
V
VI
Input voltage
–0.3
VCC + 0.3
V
VO
Output voltage
0
VCC
V
TA
Operating temperature
For commercial use
0
70
° C
For industrial use
–40
85
° C
tR
Input rise time
(5)
50
ns
tF
Input fall time
(5)
50
ns
Table 25. EP1810 Device DC Operating Conditions
Notes (6), (7)
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
High-level input voltage
2.0
VCC + 0.3
V
VIL
Low-level input voltage
–0.3
0.8
V
VOH
High-level TTL output voltage
IOH = –4 mA DC (8)
2.4
V
High-level CMOS output voltage
IOH = –0.6 mA DC (8)
3.84
V
VOL
Low-level output voltage
IOL = 4 mA DC (8)
0.45
V
II
I/O pin leakage current of dedicated
input pins
VI = VCC or ground
–10
10
µA
IOZ
Tri-state output leakage current
VO = VCC or ground
–10
10
µA



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