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EPLD bảng dữ liệu(PDF) 31 Page - Altera Corporation

tên linh kiện EPLD
Giải thích chi tiết về linh kiện  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
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EPLD bảng dữ liệu(HTML) 31 Page - Altera Corporation

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Altera Corporation
775
Classic EPLD Family Data Sheet
Notes to tables:
(1)
These values are specified in Table 15 on page 770.
(2)
See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for information on internal
timing parameters.
(3)
The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
(4)
Sample-tested only for an output change of 500 mV.
(5)
The fMAX values represent the highest frequency for pipelined data.
(6)
Measured with the device programmed as a 24-bit counter.
(7)
Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both
global and array clocking.
Table 22. EP910I Internal Timing Parameters
Symbol
Parameter
Condition
EP910I-12
EP910I-15
EP910I-25
Unit
Min
Max
Min
Max
Min
Max
tIN
Input pad and buffer delay
2.0
3.0
2.0
ns
tIO
I/O input pad and buffer delay
0.0
0.0
0.0
ns
tLAD
Logic array delay
8.0
9.0
17.0
ns
tOD
Output buffer and pad delay
C1 = 35 pF
2.0
3.0
6.0
ns
tZX
Output buffer enable delay
C1 = 35 pF
5.0
6.0
9.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
5.0
6.0
9.0
ns
tSU
Register setup time
4.0
5.0
5.0
ns
tH
Register hold time
4.0
6.0
11.0
ns
tIC
Array clock delay
12.0
12.0
14.0
ns
tICS
Global clock delay
4.0
3.0
6.0
ns
tFD
Feedback delay
1.0
1.0
3.0
ns
tCLR
Register clear time
11.0
12.0
20.0
ns



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