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Fig 8.

Write to Output Port registers

1

0

0

A2 A1 A0

0

A

S0

START condition

R/W

acknowledge

from slave

002aac220

A

SCL

SDA

A

write to port

data out

from port 0

P

9

8

7

6

5

4

3

2

1

command byte

data to port 0

DATA 0

slave address

0000010

0

STOP

condition

0.0

0.7

acknowledge

from slave

acknowledge

from slave

data to port 1

DATA 1

1.0

1.7

A

data out

from port 1

DATA VALID

Fig 9.

Write to Configuration registers

1

0

0

A2 A1 A0

0

A

S0

START condition

R/W

acknowledge

from slave

002aac221

A

SCL

SDA

A

P

9

8

7

6

5

4

3

2

1

command byte

data to register

DATA 0

slave address

0000110

0

STOP

condition

LSB

MSB

acknowledge

from slave

acknowledge

from slave

data to register

DATA 1

LSB

MSB

A