TS68HC901 datasheet(25/42 Pages) STMICROELECTRONICS

25 / 42 page

1/2

SYNC

ASYN

8 Bits

7 Bits

6 Bits

5 Bits

(* ) : Only used w ith divide- by-16 clock mode

RECEIVER INTERRUPT CHANNELS

The USART receive section is assigned two inter-

rupt channels. One indicates the buffer full condi-

tion, while the other channel indicates an error

condition. Error conditions include overrun, parity

error, synchronous found, and break. These inter-

rupting conditions correspond to the BF, OE, PE,

and F/S or B bits of the receiver status register.

These flags will function as described in 6.2.2. whe-

ther the receiver interrupt channels are enabled or

disabled.

While only one interrupt is generated per character

received, two dedicated interrupt channels allow se-

parate vector numbers to be assigned for normal

and abnormal receiver conditions. When a received

word has an error associated with it and the error in-

terrupt channel is enabled, an interrupt will be gene-

rated on the error channel only. However, if the error

channel is disabled, an interrupt for an error condi-

tion will be generated on the buffer full interrupt

channel along with interrupts produced by the buffer

full condition. The receiver status register must al-

ways be read to determine which error condition

produced the interrupt.

RECEIVER STATUS REGISTER

The receiver status register contains the receive

buffer full flag, the synchronous strip enable, the re-

ceiver enable, and various status information asso-

ciated with the data word in the receive buffer. The

RSR is latched each time a data word is transferred

to the receive buffer. RSR flags cannot change a-

gain until the data word has been read. The exception

is the character in progress flag which monitors when

a new word is being assembled in the asynchronous

character format. The receiver status register is

shown in Figure 18.

SPECIAL RECEIVE CONSIDERATIONS

RECEIVER STATUS REGISTER

RSR

(2Bh)

F/S or B

M/CIP

C LEARE D on R ESET

Figure 18 :

Certain receive conditions relating to the overrun error flag and the break defect flag require further ex-

planation. Consider the following examples :

1) A break is received while the receive buffer is full. This does not produce an overrun condition. Only

the B flag will be set after the receiver buffer is read.

2) A new word is received and the receive buffer is full. A break is received before the receive buffer is

read.

Both the B and OE flags will be set when the buffer full condition is satisfied.

Buffer Full. This bit is set when a received word is transferred to the receive buffer. This bit

is cleared when the receive buffer is read by accessing the USART data register (UDR). This

bit is read only.

SET : Received word transferred to buffer

CLEARED : Receive buffer read

Overrun Error. An overrun error occurs when a received word is due to be transferred to the

receive buffer, but the receive buffer is full. Neither the receive buffer nor the RSR is overw-

ritten. The OE bit is set after the receive buffer full condition is satisfied by reading the UDR.

This error condition will generate an interrupt to the processor. The OE bit is cleared by rea-

ding the RSR. New data words will not be assembled until the RSR is read.

TS68HC901

25/42

TS68HC901 bảng dữ liệu(PDF) 25 Page - STMicroelectronics

TS68HC901 bảng dữ liệu(HTML) 25 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

bảng dữ liệu tải về

Link URL