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TS68HC901 bảng dữ liệu(PDF) 21 Page - STMicroelectronics |
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TS68HC901 bảng dữ liệu(HTML) 21 Page - STMicroelectronics |
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21 / 42 page ![]() 7 TIMER A CONTROL REGISTER 0 TACR (19h) 0* 0* 0* TA0 RESET AC3 AC2 AC1 AC0 TIMER B CONTROL REGISTER TBCR (1Bh) 0* 0* 0* TB0 RESET BC3 BC2 BC1 BC0 C LEAR ED on R ESET 0* Unused bits, read as zero. RESET TA0/TB0 Timer’s A and B output lines (TA0 and TB0) may be forced low at any time by writing a one to the reset location in TACR and TBCR, respectively. The output will be held low only during the write operation ; at the conclusion of the operation the output will be allowed to toggle in response to a time-out pulse. When resetting TA0 and TB0, the remaining bits in the control register must be written with their previous value to avoid altering the operation mode. SET: End of write cycle which clears the bit CLEARED: MPUwrites a zero AC3-AC0 BC3-BC0 These bits are decoded to determine the timer operation mode. AC3 BC3 AC2 BC2 AC1 BC1 AC0 BC0 Operation Mode 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Timer Stopped* Delay Mode, ÷ 4 Prescaler Delay Mode, ÷ 10 Prescaler Delay Mode, ÷ 16 Prescaler Delay Mode, ÷ 50 Prescaler Delay Mode, ÷ 64 Prescaler Delay Mode, ÷ 100 Prescaler Delay Mode, ÷ 200 Prescaler Event Count Mode Pulse Width Mode, ÷ 4 Prescaler Pulse Width Mode, ÷ 10 Prescaler Pulse Width Mode, ÷ 16 Prescaler Pulse Width Mode, ÷ 50 Prescaler Pulse Width Mode, ÷ 64 Prescaler Pulse Width Mode, ÷ 100 Prescaler Pulse Width Mode, ÷ 200 Prescaler * Regardless of the operation mode, counting is inhibited when the timer is stopped. The contents of the timer’s main counter is not affected, although any residual count in the prescaler is lost. SET: End of write cycle which clears the bit CLEARED: MPUwrites a zero Figure 14 : ® TS68HC901 21/42 |
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