AD5763CSUZ datasheet(27/31 Pages) AD

27 / 31 page

Preliminary Technical Data

AD5763

Rev. PrA | Page 27 of 31

LDAC is controlled by the PC6 port output. The DAC can be

updated after each 3-byte transfer by bringing LDAC low. This

example does not show other serial lines for the DAC. For

example, if CLR were used, it could be controlled by port

output PC5.

AD5763 to 8XC51 Interface

The AD5763 requires a clock synchronized to the serial data.

For this reason, the 8XC51 must be operated in Mode 0. In this

mode, serial data enters and exits through RxD, and a shift

clock is output on TxD.

P3.3 and P3.4 are bit programmable pins on the serial port and

are used to drive SYNC and LDAC, respectively. The 8CX51

provides the LSB of its SBUF register as the first bit in the data

stream. The user must ensure that the data in the SBUF register

is arranged correctly, because the DAC expects the MSB first.

When data is to be transmitted to the DAC, P3.3 is taken low.

Data on RxD is clocked out of the microcontroller on the rising

edge of TxD and is valid on the falling edge. As a result, no glue

logic is required between this DAC and the microcontroller

interface.

8XC511

1ADDITIONAL PINS OMITTED FOR CLARITY

AD57631

SCLK

TxD

SDIN

RxD

SYNC

P3.3

LDAC

P3.4

Figure 38. AD5763 to 8XC51 Interface

The 8XC51 transmits data in 8-bit bytes with only eight falling

clock edges occurring in the transmit cycle. Because the DAC

expects a 24-bit word, SYNC (P3.3) must be left low after the

first eight bits are transferred. After the third byte has been

transferred, the P3.3 line is taken high. The DAC can be

updated using LDAC via P3.4 of the 8XC51.

AD5763 to Blackfin DSP interface

Figure 39 shows how the AD5763 can be interfaced to Anlaog

Devices Blackfin DSP. The Blackfin has an integrated SPI port

that can be connected directly to the SPI pins of the AD5763 and

programmable I/O pins that can be used to set the state of a

digital input such as the LDAC pin.

SYNC

ADSP-BF531

AD5763

SCLK

SDIN

SPISELx

SCK

MOSI

LDAC

PF10

Figure 39. AD5763 to Blackfin Interface

AD5763 to PIC16C6x/7x Interface

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the clock polarity bit set to 0. This is done

by writing to the synchronous serial port control register

(SSPCON). See the PIC16/17 Microcontroller User Manual. In

this example, I/O port RA1 is being used to pulse SYNC and

enable the serial port of the AD5763. This microcontroller

transfers only eight bits of data during each serial transfer

operation; therefore, three consecutive write operations are

needed. Figure 40 shows the connection diagram.

PIC16C6x/7x1

1ADDITIONAL PINS OMITTED FOR CLARITY

AD57631

SDO

SDI/RC4

SDIN

SDO/RC5

SCLK

SCLK/RC3

SYNC

RA1

Figure 40. AD5763 to PIC16C6x/7x Interface

EVALUATION BOARD

The AD5763 performance can be evaluated via the AD5765

evaluation board.

The AD5765 comes with a full evaluation board to aid

designers in evaluating the high performance of the part with a

minimum of effort. All that is required with the evaluation

board is a power supply and a PC. The AD5765 evaluation kit

includes a populated, tested AD5765 printed circuit board. The

evaluation board interfaces to the USB interface of the PC.

Software is available with the evaluation board, which allows

the user to easily program the AD5765. The software runs on

any PC that has Microsoft® Windows® 2000/XP installed.

An application note is available that gives full details on

operating the evaluation board.

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