AD5763

Preliminary Technical Data

Rev. PrA | Page 20 of 31

TRANSFER FUNCTION

Table 7

shows the ideal input code to output voltage

relationship for the AD5763 for both offset binary and twos

complement data coding.

Table 7. Ideal Output Voltage to Input Code Relationship

Digital Input

Analog Output

Offset Binary Data Coding

MSB

LSB

VOUTX

1111

1111

1111

1111

1000

0000

0000

0001

1000

0000

0000

0000

0 V

0111

1111

1111

1111

0000

0000

0000

0000

Twos Complement Data Coding

MSB

LSB

VOUTX

0111

1111

1111

1111

0000

0000

0000

0001

0000

0000

0000

0000

0 V

1111

1111

1111

1111

1000

0000

0000

0000

The output voltage expression for the AD5763 is given by

⎥⎦

⎤

⎢⎣

⎡

×

+

×

−

=

65536

4

2

D

V

V

V

REFIN

REFIN

OUT

where:

D is the decimal equivalent of the code loaded to the DAC.

ASYNCHRONOUS CLEAR (CLR)

CLR is a negative edge triggered clear that allows the outputs to

be cleared to either 0 V (twos complement coding) or negative

full scale (offset binary coding). It is necessary to maintain CLR

low for a minimum amount of time (see Figure 2) for the

operation to complete. When the CLR signal is returned high,

the output remains at the cleared value until a new value is

programmed. If at power-on, CLR is at 0 V, then all DAC

outputs are updated with the clear value. A clear can also be

initiated through software by writing the command 0x04XXXX

to the AD5763.

Table 8. AD5763 Input Register Format

MSB

LSB

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R/W

0

REG2

REG1

REG0

A2

A1

A0

DATA

Table 9. Input Register Bit Functions

Bit

Description

R/W

Indicates a read from or a write to the addressed register.

REG2, REG1, REG0

Used in association with the address bits to determine if a read or write operation is to the data register, offset

register, gain register, or function register.

REG2

REG1

REG0

Function

0

0

0

Function Register

0

1

0

Data Register

0

1

1

Coarse Gain Register

1

0

0

Fine Gain Register

1

0

1

Offset Register

A2, A1, A0

These bits are used to decode the DAC channels.

A2

A1

A0

Channel Address

0

0

0

DAC A

0

0

1

DAC B

1

0

0

BOTH DACs

D15:D0

Data Bits.