AD5763CSUZ datasheet(26/31 Pages) AD

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AD5763

Preliminary Technical Data

Rev. PrA | Page 26 of 31

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure the

rated performance. The printed circuit board on which the

AD5763 is mounted should be designed so that the analog and

digital sections are separated and confined to certain areas of the

board. If the AD5763 is in a system where multiple devices

require an AGND-to-DGND connection, the connection should

be made at one point only. The star ground point should be

established as close as possible to the device. The AD5763 should

have ample supply bypassing of 10 µF in parallel with 0.1 µF on

each supply located as close to the package as possible, ideally

right up against the device. The 10 µF capacitors are the tantalum

bead type. The 0.1 µF capacitor should have low effective series

resistance (ESR) and low effective series inductance (ESI) such as

the common ceramic types, which provide a low impedance path

to ground at high frequencies to handle transient currents due to

internal logic switching.

The power supply lines of the AD5763 should use as large a

trace as possible to provide low impedance paths and reduce

the effects of glitches on the power supply line. Fast switching

signals, such as clocks, should be shielded with digital ground

to avoid radiating noise to other parts of the board, and should

never be run near the reference inputs. A ground line routed

between the SDIN and SCLK lines helps reduce crosstalk

between them (not required on a multilayer board, which has a

separate ground plane, however, it is helpful to separate the

lines). It is essential to minimize noise on the reference inputs,

because it couples through to the DAC output. Avoid crossover

of digital and analog signals. Traces on opposite sides of the

board should run at right angles to each other. This reduces the

effects of feedthrough on the board. A microstrip technique is

recommended, but not always possible with a double-sided

board. In this technique, the component side of the board is

dedicated to ground plane, and signal traces are placed on the

solder side.

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to provide

an isolation barrier between the controller and the unit being

controlled to protect and isolate the controlling circuitry from

any hazardous common-mode voltages that might occur.

Isocouplers provide voltage isolation in excess of 2.5 kV. The

serial loading structure of the AD5763 makes it ideal for

isolated interfaces because the number of interface lines is kept

to a minimum. Figure 36 shows a 4-channel isolated interface

to the AD5763 using an ADuM1400. For more information, go

to www.analog.com.

VIA

SERIAL CLOCK OUT

TO SCLK

VOA

ENCODE

DECODE

VIB

SERIAL DATA OUT

TO SDIN

VOB

ENCODE

DECODE

VIC

SYNC OUT

TO SYNC

VOC

ENCODE

DECODE

VID

CONTROL OUT

TO LDAC

VOD

ENCODE

DECODE

µCONTROLLER

ADuM14001

1ADDITIONAL PINS OMITTED FOR CLARITY

Figure 36. Isolated Interface

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5763 is via a serial bus

that uses a standard protocol that is compatible with micro-

controllers and DSP processors. The communications channel

is a 3-wire (minimum) interface consisting of a clock signal, a

data signal, and a synchronization signal. The AD5763 requires

a 24-bit data-word with data valid on the falling edge of SCLK.

For all the interfaces, the DAC output update can be done

automatically when all the data is clocked in, or it can be done

under the control of LDAC. The contents of the DAC register

can be read using the readback function.

AD5763 to MC68HC11 Interface

Figure 37 shows an example of a serial interface between the

AD5763 and the MC68HC11 microcontroller. The serial

peripheral interface (SPI) on the MC68HC11 is configured for

master mode (MSTR = 1), clock polarity bit (CPOL = 0), and the

clock phase bit (CPHA = 1). The SPI is configured by writing to the

SPI control register (SPCR) (see the MC68HC11 User Manual).

SCK of the MC68HC11 drives the SCLK of theAD5763, the MOSI

output drives the serial data line (DIN) of the AD5744/AD5763,

and the MISO input is driven from SDO. The SYNC is driven from

one of the port lines, in this case, PC7.

When data is being transmitted to the AD5763, the SYNC line

(PC7) is taken low and data is transmitted MSB first. Data

appearing on the MOSI output is valid on the falling edge of

SCK. Eight falling clock edges occur in the transmit cycle, so, in

order to load the required 24-bit word, PC7 is not brought high

until the third 8-bit word has been transferred to the DAC

input shift register.

MC68HC111

1ADDITIONAL PINS OMITTED FOR CLARITY

AD57631

SDO

MISO

SDIN

MOSI

SCLK

SCK

SYNC

PC7

Figure 37. AD5763 to MC68HC11 Interface

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