TEA2028 datasheet(27/47 Pages) STMICROELECTRONICS

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Frame

Sync.

Separator

50/60Hz

Output

Frame

Sawtooth

Frame

Yoke

→ I

Power

Amplifier

Frame

Sawtooth

Generator

I60

50/60Hz

Reset

≥ 1

Frame Logic

Free

Reset

H/2

Reference

Block

Composite

Sync.

Top of Picture

Bottom of Picture

Figure 51 : Block Diagram of the Vertical Deflection Stage

V.6.1 - Frame sync extraction

The main duty of this stage is to extract the frame

sync pulses contained in composite sync signal.

Frame

Sync.

µA

C = 35pF

I C

I D

2.8V

Composite

Sync.

5.6V

2.8V

Figure 52 : Sync. Extractor Block Diagram

Two current generators are used to charge and

discharge the integrated capacitor ”C”. The dis-

charge generator (IC +ID) is driven by the compos-

ite sync signal.

The

∆VC across capacitor is : −

⋅ tSYNC

During frame trace, the capacitor is discharged at

each line sync pulse thereby generating a

∆Vof

-0.94V with respect to 5.6V and then recovers the

charge by current ”IC”. The comparator output re-

mains low.

The discharge time is 27

µs at the first line sync

inversion applied to comparator input. The voltage

”VC” then falls from 5.6V to 0.2V and triggers the

comparator ”C0” which will deliver a frame sync

pulse when ”VC” crosses the 2.8V level.

The overall arrangement behaves as an integrator

and will therefore suppress any noise susceptible

to be present on input signal.

An external capacitor Pin 20 can be added to the

integrated capacitor C to increase the frame sync

time constant.

V.6.2 - Frame saw-tooth generator

Frame Sawtooth

Output

2.2k

Ω

470nF

2.7M

Ω

(200V)

60Hz

Frame

Reset

(64

µs)

FRAME LOGIC

BLOCK

∆I

Figure 53

The frame saw-tooth is generated by an external

RC network on Pin 5.

The time constant ”R5

⋅ C5” is much higher than

the frame period. Therefore, the generated saw-

tooth is quite linear.

The network is discharged by an internal transistor,

controlled by the frame logic block.

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