TEA2028 datasheet(22/47 Pages) STMICROELECTRONICS

22 / 47 page

A. BLOCK DIAGRAM

”V’OUT” will set the flip-flop thereby allowing the

capacitor ”C1” to be charged by current ”IC” deliv-

ered through current generator. The voltage across

capacitor begins rising until it reaches ”VREF”. At

this time, comparator ”C” is triggered, the output of

which will in turn reset the flip-flop. The capacitor

”C” is consequently discharged by current ID -IC.

≥ 1

VREF

144

µA

380

µA

µs

Auto-Set

Signal

V10

To Output

Stage

t’OUT

T 10

t’

OUT

V’OUT

Window

Figure 42

B. T10 CALCULATION (see Figure 43)

T10 =

⋅ ∆V1

⋅ VREF

”IC” is a fraction of ”IREF” on pin 14

IC =

IREF

VREF

α ⋅ R14

= 144

µA

⇒ T10 = α ⋅ R14 ⋅ C1 = 2.64 ⋅ R14 ⋅ C1

with R14 = 3.32k

Ω, C1 = 3.3nF ⇒ T10 =29µs

-T10 is independent from temperature and VCC

α has a maximum dispersion of ± 3% from device

to device

C. 16

µs WINDOW

This window is generated by the line logic circuitry

and sets the maximum phase variations of the

output signal ”V10”.

Also, for protection purposes, should ”V16” voltage

equal ”0”, the output signal will be always present

and have a maximum phase shift of 16

µs with

respect to the falling-edge of the line saw-tooth.

D. AUTO-SET TO ”1”

To provide protection, this function will trigger the

f lip -flop if the modulato r is d isa bl ed, i. e.

V16 >V13(MAX).

Maximum

Phase

Variation

VREF

(1.26V)

V’

OUT

µs

Auto-Set

Set

Window

µs

T10

V10

Figure 43

E. MAXIMUM ”T10” VALUE AS A FUNCTION

OF ”C1”

T10 (Min.) :16

µs (window) + 4µs (auto set) = 20µs

⇒C1(Min.) = 2.3nF

T10 (Max.) : for

⋅ VREF

− IC

⋅ VREF

≤ 64µs

⇒T10 (Max.) =40µs ⇒ C1(Max.) = 4.6nF

For normal operation, C1 value has to be chosen

between 2.3nF and 4.6nF.

If Pin 1 is grounded, output signal (Pin 10) is

inhibited and goes high.

V.5.2.5 - Line output stage & inhibitions

≥ 1

T 10

Output

Line ”DRIVE”

Line Flyback

Input

T10

Monostable

≥ 1

Logic 1 for

VCC <6V

Logic 1 for

Security at Pin 28

Inhibition

Power

Ground

Figure 44

TEA2028 - TEA2029 APPLICATION NOTE

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