TDA9109A datasheet(29/47 Pages) STMICROELECTRONICS

tên linh kiện	TDA9109A

Giải thích chi tiết về linh kiện	LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR

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TDA9109A

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Figure 5.

Figure 6.

The last feature performed is the removal of equal-

ization pulses to avoid parasitic pulses on the

phase comparator (which would be disturbed by

missing or extraneous pulses). This last feature is

switched on/off by sub-address 0F D8. By default

[0], equalization pulses will not be removed.

2.2 PLL1

The PLL1 consists of a phase comparator, an ex-

ternal filter and a voltage-controlled oscillator

(VCO).The phase comparator is a “phase frequen-

cy” type designed in CMOS technology. This kind

of phase detector avoids locking on wrong fre-

quencies. It is followed by a “charge pump”, com-

posed of two current sources : sunk and sourced

(typically I =1 mA when locked and I = 140

µA

when unlocked). This difference between lock/un-

lock allows smooth catching of the horizontal fre-

quency by PLL1. This effect is reinforced by an in-

ternal original slow down system when PLL1 is

locked, avoiding the horizontal frequency chang-

ing too quickly. The dynamic behavior of PLL1 is

fixed by an external filter which integrates the cur-

rent of the charge pump. A “CRC” filter is generally

used (see Figure 7)

Figure 7.

Ω

4.7

µF

PLL1F

10nF

1.8k

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