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7721 Group User’s Manual

13-16

DMA CONTROLLER

13.2 Block description

13.2.12 DMAi control register

Figure 13.2.8 shows the structure of the DMAi control register. For bits 0–4, refer to section “13.3.2

(1) DMA request sources.”

(1)

_________

DMAACKi

validity bit (bit 5)

_________

When this bit is set to “1,” the corresponding pin of port P9 serves as the DMAACKi pin and

outputs “L” during a DMA transfer. For details, refer to each timing diagram of section “13.5

Single transfer mode” through section “13.8 Link array chain transfer mode.”

Bit

Bit name

At reset

Functions

DMA0 control register (Address 1FCE16)

DMA1 control register (Address 1FDE16)

DMA2 control register (Address 1FEE16)

DMA3 control register (Address 1FFE16)

Note: When a certain source other than an external source is selected by bits 0 to 3 or when

the cycle-steal transfer mode is selected, set bit 4 to “0.”

Level sense can be selected only when both of the external source and the burst

transfer mode are selected.

0 0 0 0 : Do not select.

0 0 0 1 : External source (DMAREQi)

0 0 1 0 : Software DMA source

0 0 1 1 : Timer A0

0 1 0 0 : Timer A1

0 1 0 1 : Timer A2

0 1 1 0 : Timer A3

0 1 1 1 : Timer A4

1 0 0 0 : Timer B0

1 0 0 1 : Timer B1

1 0 1 0 : Timer B2

1 0 1 1 : UART0 receive

1 1 0 0 : UART0 transmit

1 1 0 1 : UART1 receive

1 1 1 0 : UART1 transmit

1 1 1 1 : A-D conversion

7, 6

DMA request source select bits

(Note)

Edge sense/Level sense select

bit (Used when external source

and burst transfer mode are

selected) (Note)

DMAACKi validity bit

0 : Invalid (The pin functions as a

programmable I/O port.)

1 : Valid

(The pin functions as DMAACKi.)

Undefined

–

0 : Edge sense (Falling edge)

1 : Level sense (“L” level)

Nothing is assigned.

b3b2b1b0

Fig. 13.2.8 Structure of DMAi control register

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