7721 datasheet(242/577 Pages) RENESAS

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7721 Group User’s Manual

11–39

SERIAL I/O

11.4 Clock asynchronous serial I/O (UART) mode

Fig. 11.4.7 Example of transmit timing when transfer data length = 8 bits (when parity enabled,

____

selecting 1 stop bit, selecting CTS function)

Fig. 11.4.6 Example of transmit timing when transfer data length = 8 bits (when parity enabled,

____

selecting 1 stop bit, not selecting CTS function)

D0 D1 D2 D3

D4 D5 D6

D0 D1

D0 D1 D2 D3 D4 D5 D6 D7

TENDi

TxDi

TENDi: Next transmit conditions are examined when this signal level is “H.”

(TENDi is an internal signal. Accordingly, it cannot be read from the external.)

Tc: 16(n + 1)/fi or 16(n + 1)/fEXT

fi: BRGi’s count source frequency (f2, f16, f64, f512)

fEXT: BRGi’s count source frequency (external clock)

n: Value set in BRGi

Transfer clock

Transmit enable bit

Transmit buffer

empty flag

Transmit register

empty flag

UARTi transmit

interrupt request bit

Data is set in UARTi transmit buffer register.

Start bit

Parity bit

Cleared to “0” when interrupt request is accepted or cleared by software.

The above timing diagram applies when

the following conditions are satisfied:

q Parity enabled

q 1 stop bit

q CTS function not selected

UARTi transmit register

UARTi transmit buffer register

Stopped because transmit enable bit = “0”

Stop bit

The above timing diagram applies

when the following conditions are

satisfied:

q Parity enabled

q 1 stop bit

q CTS function selected

D0 D1 D2 D3

D4 D5 D6

D0 D1

D0 D1 D2 D3 D4 D5 D6 D7

P SP

TENDi

TxDi

TENDi: Next transmit conditions are examined when this signal level is “H.”

(TENDi is an internal signal. Accordingly, it cannot be read from the external.)

Tc = 16(n + 1)/fi or 16(n + 1)/fEXT

fi: BRGi’s count source frequency (f2, f16, f64, f512)

fEXT: BRGi’s count source frequency (external clock)

n: Value set in BRGi

Transfer clock

Transmit buffer

empty flag

Transmit register

empty flag

UARTi transmit

interrupt request bit

Data is set in UARTi transmit buffer register.

Start bit

Parity

bit

Cleared to “0” when interrupt request is accepted or cleared by software.

UARTi transmit register

Stopped because transmit

enable bit = “0”

Stop

bit

UARTi transmit buffer register

Transmit enable bit

CTSi

Stopped because CTS = “H”

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