7721 datasheet(233/577 Pages) RENESAS

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SERIAL I/O

7721 Group User’s Manual

11–30

11.3 Clock synchronous serial I/O mode

[Precautions for clock synchronous serial I/O mode]

1. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when

performing only reception, transmit operation (setting for transmission) must be performed. In this case,

dummy data is output from the TxDi pin.

2. When receiving, simultaneously set the receive enable bit and the transmit enable bit to “1.”

3. When receiving data, write dummy data to the low-order byte of the UARTi transmit buffer register for

each reception of 1-byte data.

4. When selecting an external clock, satisfy the following 3 conditions with the input to the CLKi pin = “H”

level.

Set the transmit enable bit to “1.”

Write transmit data to the UARTi transmit buffer register.

____

Input “L” level to the CTSi pin (when selecting the CTS function).

Set the receive enable bit to “1.”

Set the transmit enable bit to “1.”

Write dummy data to the UARTi transmit buffer register.

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