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TIMER A

7721 Group User’s Manual

8–37

8.5 One-shot pulse mode

[Precautions for one-shot pulse mode]

1. If the count start bit is cleared to “0” during counting, the counter becomes as follows:

•The counter stops counting, and the reload register’s contents are reloaded into the counter.

•The TAjOUT pin’s output level becomes “L.”

•The timer Aj interrupt request bit is set to “1.”

2. A one-shot pulse is output synchronously with an internally generated count source. Accordingly, when

selecting an external trigger, there will be a delay equivalent to one cycle of the count source at maximum

from when a trigger is input to the TAjIN pin until a one-shot pulse is output.

Note: The above applies when an external trigger (falling edge of TAjIN pin’s input signal) is selected.

TAjIN pin’s

input signal

Count

source

Trigger input

Starts outputting of one-shot pulse

One-shot pulse

output from

TAjOUT pin

Fig. 8.5.6 Output delay in one-shot pulse output

3. When the timer’s operating mode is set by one of the following procedures, the timer Aj interrupt request

bit is set to “1.”

qWhen the one-shot pulse mode is selected after reset

qWhen the operating mode is switched from the timer mode to the one-shot pulse mode

qWhen the operating mode is switched from the event counter mode to the one-shot pulse mode

Accordingly, when using the timer Aj interrupt (interrupt request bit), be sure to clear the timer Aj interrupt

request bit to “0” after the above setting.

4. Don not set “000016” to the timer Aj register.

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