SH7721 datasheet(330/1524 Pages) RENESAS

330 / 1524 page

Section 8

Interrupt Controller (INTC)

Rev. 3.00 Jan. 18, 2008 Page 268 of 1458

REJ09B0033-0300

8.4.4

PINT Interrupts

PINT interrupts are input by level from pins PINT0 to PINT15. The priority level of PINT0 to

PINT7 (PINTA) and PINT8 to PINT15 (PINTB) can be set by the interrupt priority level register

H (IPRH) in a range from 0 to 15. The PINT interrupt level should be retained until the interrupt

processing starts after an interrupt request has been accepted.

The interrupt mask bits I3 to I0 in the status register (SR) are not affected by the PIN interrupt

processing routine.

While an RTC clock is supplied, recovery from a standby state on a PINT interrupt is possible if

the interrupt level is higher than that set in the I3 to I0 bits of the SR register.

8.4.5

On-Chip Peripheral Module Interrupts

On-chip peripheral module interrupts are generated by the following modules:

• DMA controller (DMAC)

• I2C bus interface (IIC)

• Smart card interface (SIM)

• Compare match timer (CMT)

• Timer unit (TMU)

• Timer pulse unit (TPU)

• Watchdog timer (WDT)

• User debugging interface (H-UDI)

• LCD controller (LCDC)

• Secure sockets layer (SSL)

• Analog front end interface (AFEIF)

• USB function controller (USBF)

• USB host controller (USBH)

• Bus state controller (BSC)

• Serial I/O with FIFO 0 (SIOF0)

• Serial I/O with FIFO 1 (SIOF1)

• Serial communication interface with FIFO 0 (SCIF0)

• Serial communication interface with FIFO 1 (SCIF1)

• MultiMediaCard interface (MMC)

• SD host interface (SDHI)

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