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SH7721 bảng dữ liệu(PDF) 269 Page - Renesas Technology Corp |
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SH7721 bảng dữ liệu(HTML) 269 Page - Renesas Technology Corp |
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269 / 1524 page ![]() Section 5 Cache Rev. 3.00 Jan. 18, 2008 Page 207 of 1458 REJ09B0033-0300 5.3.2 Read Access (1) Read Hit In a read access, instructions and data are transferred from the cache to the CPU. The LRU i s updated to indicate that the hit way is the most recently hit way. (2) Read Miss An external bus cycle starts and the entry is updated. The way to be replaced is shown in table 5.4. Entries are updated in 16-byte units. When the desired instruction or data that caused the miss is loaded from external memory to the cache, the instruction or data is transferred to the CPU in parallel with being loaded to the cache. When it is loaded to the cache, the U bit is cleared to 0 and the V bit is set to 1 to indicate that the hit way is the most recently hit way. When the U bit for the entry which is to be replaced by entry updating in write-back mode is 1, the cache-update cycle starts after the entry is transferred to the write-back buffer. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte units. 5.3.3 Prefetch Operation (1) Prefetch Hit The LRU is updated to indicate that the hit way is the most recently hit way. The other contents of the cache are not changed. Instructions and data are not transferred from the cache to the CPU. (2) Prefetch Miss Instructions and data are not transferred from the cache to the CPU. The way that is to be replaced is shown in table 5.3. The other operations are the same as those for a read miss. 5.3.4 Write Access (1) Write Hit In a write access in write-back mode, the data is written to the cache and no external memory write cycle is issued. The U bit of the entry that has been written to is set to 1, and the LRU is updated to indicate that the hit way is the most recently hit way. In write-through mode, the data is written to the cache and an external memory write cycle is issued. The U bit of the entry that has been written to is not updated, and the LRU is updated to indicate that the hit way is the most recently hit way. |
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