SH7721 datasheet(245/1524 Pages) RENESAS

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Section 4 Memory Management Unit (MMU)

Rev. 3.00 Jan. 18, 2008 Page 183 of 1458

REJ09B0033-0300

Table 4.1

Access States Designated by D, C, and PR Bits

Privileged Mode

User Mode

Reading

Writing

Reading

Writing

D bit

Permitted

Initial page write

exception

Permitted

Initial page write

exception

Permitted

C bit

Permitted

(no caching)

Permitted

(no caching)

Permitted

(no caching)

Permitted

(no caching)

Permitted

(with caching)

Permitted

(with caching)

Permitted

(with caching)

Permitted

(with caching)

PR bit

Permitted

TLB protection

violation

exception

TLB protection

violation

exception

TLB protection

violation exception

Permitted

TLB protection

violation

exception

TLB protection

violation exception

Permitted

TLB protection

violation

exception

Permitted

TLB protection

violation exception

Permitted

4.4

MMU Functions

4.4.1

MMU Hardware Management

There are two kinds of MMU hardware management as follows.

1. The MMU decodes the virtual address accessed by a process and performs address translation

by controlling the TLB in accordance with the MMUCR settings.

2. In address translation, the MMU receives page management information from the TLB, and

determines the MMU exception and whether the cache is to be accessed (using the C bit). For

details of the determination method and the hardware processing, see section 4.5, MMU

Exceptions.

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