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SH7721 bảng dữ liệu(PDF) 231 Page - Renesas Technology Corp

tên linh kiện SH7721
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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SH7721 bảng dữ liệu(HTML) 231 Page - Renesas Technology Corp

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Section 4 Memory Management Unit (MMU)
Rev. 3.00 Jan. 18, 2008 Page 169 of 1458
REJ09B0033-0300
(c)
P2 Area
The P2 area cannot be accessed via the cache and cannot be address-translated by the TLB.
Whether the MMU is enabled or not, replacing the upper three bits of an address in this area with
0s creates the address in the corresponding physical address space.
(d)
P4 Area
The P4 area is mapped to the on-chip I/O of this LSI. This area cannot be accessed via the cache
and cannot be address-translated by the TLB. Figure 4.4 shows the configuration of the P4 area.
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
P0 area
Cacheable
Address translation possible
U0 area
Cacheable
Address translation possible
Uxy area*
P1 area
Cacheable
Address translation not possible
P2 area
Non-Cacheable
Address translation not possible
P3 area
Cacheable
Address translation possible
P4 area
Non-Cacheable
Address translation not possible
Address error
Address error
H'0000 0000
H'8000 0000
H'A500 0000
H'A5FF FFFF
H'FFFF FFFF
H'0000 0000
Privileged mode
User mode
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 7
Area 6
External Address
Space
Note: Only exists when SR.DSP = 1
256
256
Figure 4.2 Virtual Address Space (MMUCR.AT = 1)



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